The present invention relates to a semiconductor device including resistive random access memory (ReRAM) elements.
In semiconductor integrated circuits, one-time programmable (OTP) memory to which data can be written only once is generally used to store memory redundancy information. The memory elements used for OTP memory includes, for example, electrically writable fuse elements and antifuse elements.
FIG. 1 is a conceptual diagram showing a typical MOS type (gate insulating film destruction type) antifuse element. Like in MOS transistors and MOS capacitors, a gate electrode 3 is formed over a P well 1 via a gate insulating film 2. The MOS type antifuse element is a two-terminal element having a first terminal T1 and a second terminal T2. In the example shown in FIG. 1, the gate electrode 3 is coupled to the first terminal T1 and a source/drain diffusion layer is coupled to the second terminal T2.
This MOS type antifuse element is a type of ReRAM element which stores data making use of a resistance change. To be more concrete, the gate insulating film 2 can be broken down by applying a high voltage between the first terminal T1 and the second terminal T2. Depending on whether or not the gate insulating film 2 is broken down, the conduction (resistance) between the first terminal T1 and the second terminal T2 changes between two states which correspond to data “0” and data “1”. For example, as shown in FIG. 1, a non-conducting state (an unwritten state) with the gate insulating film 2 unbroken corresponds to data “0” and a conducting state (a written state) with the gate insulating film 2 broken down corresponds to data “1”.
When data is to be read, a read voltage is applied between the first terminal T1 and the second terminal T2. When an element current flowing between the first terminal T1 and the second terminal T2 exceeds a threshold value, the data stored is determined to be “1”; otherwise the data stored is determined to be “0”. When the data stored is “1” with an element current flowing between the first terminal T1 and the second terminal T2, a substrate current Isub flows through the P well 1 as shown in FIG. 1.
FIG. 2 shows a configuration of a general memory cell array including antifuse elements (see FIG. 3 of Japanese Unexamined Patent Publication No. Hei 08 (1996)-316427. A memory cell 305 for storing one bit of data has an antifuse element 301 and a selection transistor 302. The gate of the selection transistor 302 is coupled to a word line 303. One end of the antifuse element 301 is coupled to the drain of the selection transistor 302. The other end of the antifuse element 301 is coupled to a bit line 304. The word line 303 is coupled to a word decode circuit 306. The bit line 304 is coupled to a bit decode circuit 307.
In Japanese Unexamined Patent Publication No. Hei 08 (1996)-316427, a circuit configuration in which a selection transistor is shared by plural antifuse elements is also disclosed. In such a configuration, too, the antifuse elements can each function as an individual memory cell to store one bit of data. A similar circuit configuration is also disclosed in each of U.S. Pat. No. 6,410,352 and U.S. Pat. No. 6,590,797.
In Japanese Unexamined Patent Publication No. 2010-146665, a redundancy technique used in resistance nonvolatile semiconductor memory is disclosed.
In U.S. Pat. No. 5,940,545, a technique to detect faint photoemission attributable to a current flowing in a semiconductor layer during operation of a semiconductor integrated circuit is disclosed.